Our client is seeking
a highly experienced ASIC Verification Engineer to help develop and verify complex digital ASICs in a collaborative, geographically diverse environment.
Key Responsibilities-
Lead the development of verification infrastructure for advanced ASIC designs
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Create System Verilog/UVM-based protocol and traffic generators/checkers
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Develop and execute test plans based on functional and standards requirements
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Define, develop, and run self-checking tests for complex digital ASICs
Required Qualifications-
Bachelor’s degree in computer science or electrical engineering (master’s preferred)
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8+ years of experience in ASIC verification
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Proven experience in developing and implementing test plans at block or sub-chip levels
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Proficiency in System Verilog and scripting languages such as Python
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Deep understanding of UVM methodology
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Experience with assertions, functional coverage, code coverage, and formal verification tools
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Strong communication skills and ability to work effectively in a distributed team
Preferred Skills-
Knowledge of DSP and/or FEC technologies
