Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.
You have spent years where electrical meets optical, where theory meets silicon, and where a good model saves months of debug. You know that SerDes at 128Gbps or 200Gbps is about margin, jitter, equalization, and decisions that either hold together or fall apart when the link goes live. Building MATLAB models that actually predicted lab results has taught you the difference between what should work and what does work, and you understand why that gap matters more than most people realize.
Talking CDR loop dynamics with analog designers feels natural. So does explaining link budgets to customers who need to understand why their system will or will not close. You do not need perfect specs to start. You build the model or algorithm that moves the design forward, then refine it when reality provides feedback. When silicon measurements diverge from simulation, you are the one who figures out why, not by guessing but by systematically working through the physics and the implementation until the picture is clear.
At Synopsys, you will work on SerDes IP powering PCIe Gen6+ and 200G+ Ethernet in optical systems that ship. The team is deep, the problems are hard, and what you architect matters.
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Build and maintain SerDes system models in MATLAB and Simulink for NRZ and PAM4 optical links, covering transmitter, receiver, channel, and equalization behavior
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Run sign-off simulations across PCIe 128Gbps+ and Ethernet 200Gbps+ protocols to verify performance against spec and identify margin risks before tapeout
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Design calibration and adaptation algorithms that tune transceiver performance in real time, balancing convergence speed, stability, and power
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Correlate simulation results with silicon measurements, iterate models to close gaps, and document what changed and why
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Support customers on system-level performance questions, optical integration challenges, and link budget analysis for their specific channel and module configurations
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Work with analog designers on circuit implementation tradeoffs, digital teams on DSP and calibration logic, and hardware engineers on lab bringup and characterization
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Review architecture proposals, protocol updates, and design specs to ensure system-level feasibility and flag issues early
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Your models define what gets built, catching margin issues, equalization limits, and timing problems before silicon respins cost months and budget
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You shape SerDes IP performance for hyperscale data centers, AI training clusters, and next-generation networking infrastructure where every dB and every picosecond matters
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Your calibration and adaptation algorithms enable real-time tuning that improves yield, reduces test time, and expands the operating envelope across process and temperature
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You close the simulation-to-silicon gap, reducing customer debug cycles and giving them confidence that the IP will work in their system the first time
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Your customer engagements surface real-world constraints and edge cases that inform next-generation architecture decisions and roadmap priorities
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You help Synopsys maintain technical leadership in high-speed optical SerDes, a market where performance and credibility are won one successful tapeout at a time
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You mentor engineers across analog, digital, and system domains, raising the bar on how modeling, correlation, and system thinking get done across the IP group
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M.Sc. or Ph.D. in Electrical Engineering, Computer Engineering, or a related field with focus on high-speed communications, analog circuits, or signal processing
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Deep expertise in one or more of the following: optical specifications like RTLR and LINEAR, SerDes modeling in MATLAB or Simulink for IMDD optical links, high-speed analog CMOS design, DSP techniques for SerDes equalization and timing recovery, or communications theory including equalization, coding, and noise filtering
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Experience analyzing and closing link budgets for NRZ or PAM4 signaling at 100Gbps or higher, accounting for transmitter impairments, channel loss, reflection, crosstalk, and receiver noise
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Hands-on work with SerDes transmitter and receiver architectures, equalization techniques such as FFE, DFE, and CTLE, or CDR loop dynamics and jitter tolerance
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Ability to correlate models with silicon measurements, debug discrepancies systematically, and update models to reflect real-world behavior
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Experience with photonics modeling, optical interfacing, or lab testing and characterization is a plus
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Familiarity with C, Verilog-A, or SystemVerilog for co-simulation or algorithm prototyping is a plus
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You sit in circuit-level design reviews, absorb the tradeoffs being discussed, and know exactly what to update in your model to reflect the new reality
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You ask whether corner cases are covered, whether the channel models are realistic, and whether the margin will actually hold when the system is in production and temperature is drifting
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You can explain a link budget to a customer or a non-expert colleague clearly, showing not just the numbers but why they matter and where the risk is
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You manage multiple protocol sign-offs, customer escalations, and internal design iterations at once without dropping threads or losing track of what is blocking what
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You push back when specs are unclear, when assumptions do not match the physics, or when a proposed solution will not scale to the next speed grade
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You connect dots across photonics, analog design, DSP, and protocol layers, seeing how a change in one domain ripples through the others
You will be part of an R&D team developing bleeding edge NRZ and PAM4 SerDes transceivers targeting PCIe 128Gbps+ and Ethernet 200Gbps+ specifications for optical applications. You will work with a cross-functional team of analog and digital designers and hardware engineers across all stages of development, from modeling and sign-off to silicon correlation and customer support. This team is part of Synopsys' Silicon IP business, which delivers the world's broadest portfolio of IP to help customers integrate more capabilities, meet unique performance and power requirements, and get differentiated products to market quickly with reduced risk.
We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.
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