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Job Description:
Description du poste
Le groupe de développement Mixed Signal est responsable de la livraison d’IP analogiques et mixtes aux divisions produits de Microchip. Nous travaillons avec des procédés CMOS de pointe pour produire des circuits intégrés analogiques destinés aux applications filaires. Nous permettons la mise en œuvre de technologies qui permettent aux produits Microchip d’interagir avec le monde extérieur.
En tant que membre du groupe de développement Mixed Signal, le candidat participera au support et au débogage des IP mixtes, notamment des PLL, des SERDES haute vitesse, des CAN, des CNA et d’autres blocs de base analogiques.
Responsabilités
- Définir les exigences pour les IP mixtes en collaboration avec les architectes SoC
- Collaborer avec les fournisseurs d’IP pour personnaliser les solutions IP et finaliser le cahier des charges (SOW)
- Gérer les processus d’intégration des IP, y compris la pré-licence, l’assurance qualité post-acquisition, l’intégration et les revues de validation
- Assurer le support des IP mixtes après la phase de tape-out, y compris les tests en laboratoire, la mise en service client et le débogage
- Participation active aux tests en laboratoire, au support et au débogage des blocs mixtes et SERDES
- Prise en charge des spécifications des circuits et des systèmes
- Concevoir des circuits intégrés analogiques et mixtes en technologie CMOS
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Job Description
The Mixed Signal Development Group is responsible for delivering analog and Mixed-Signal IPs to product divisions within Microchip. We work with leading edge CMOS processes to produce analog integrated circuits for wireline applications. We enable technology that allows Microchip’s products to interface to the outside world.
As a member of the Mixed-Signal Development Group, the candidate will be engaged in the mixed-signal IP support and debug of PLLs, high speed SERDES, ADCs, DACs, and other analog building blocks.
Responsibilities
Define the requirements for Mixed-Signal IPs in discussion with the SoC architects
Collaborate with IP vendors to customize IP solutions and finalize Statement of Work (SOW)
Manage IP intake processes, including pre-licensing and post-acquisition QA, integration, and sign-off reviews
Support Mixed-Signal IP through post-tape out phase, including lab testing, customer bring-up and debug
Active involvement in lab testing, support and debug of mixed-signal and SERDES blocks
Ownership of circuit and system specifications
Design CMOS analog and mixed-signal integrated circuits
Requirements/Qualifications:
Diplôme de licence en génie électrique ou dans un domaine connexe, avec une solide expérience en analogique/mixtes et au moins 10 ans d’expérience en conception de circuits CMOS mixtes, ou un master avec au moins 7,5 ans d’expérience dans ce domaine.
- Excellente compréhension des étapes du flux de conception analogique mixte, y compris l’architecture, la conception et l’intégration
- Expérience avec les circuits SERDES haute vitesse et/ou PLL
- Expérience avec les simulateurs de circuits (HSPICE, Spectre, etc.)
- Une expérience avec les protocoles PCIe, SAS, SATA et Ethernet est un atout
- Une expérience avec les technologies chiplet est un atout
- Bonne compréhension de la physique des dispositifs et des concepts de base ESD/Latch-up
- Excellentes compétences en communication écrite et orale
- Capacité à travailler en équipe
- Esprit innovant et créatif
- Capacité à s’adapter rapidement à de nouveaux projets
Maîtrise de l’anglais (à l’écrit et à l’oral) requise pour ce poste. Les candidats doivent être capables de communiquer efficacement en anglais avec les collègues, les clients et les parties prenantes, ainsi que de lire et comprendre les documents et instructions liés au travail.
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Bachelor’s degree in electrical engineering or related field with strong analog/mixed-signal background and at least 10 years of mixed-signal CMOS circuit design experience, or a Master’s degree with at least 7.5 years of such experience.
Deep understanding of the mixed-signal analog design flow steps including architecture, design, and integration
Experience with high-speed SERDES and/or PLL circuits
Experience with circuit simulators (HSPICE, Spectre, etc.)
Experience working with PCIe, SAS, SATA and Ethernet protocols is a plus
Experience working with chiplet technologies is a plus
Possess understanding of device physics and basic ESD/Latch-up concepts
Strong written and oral communication skills
Ability to work in a team environment
Innovative and creative thinker
Ability to quickly ramp on new projects
Travel Time:
0% - 25%
Pay Range:
We offer a total compensation package that ranks among the best in the industry. It consists of competitive base pay, restricted stock units, and quarterly bonus payments. In addition to these components, our package includes health benefits that begin day one, retirement savings plans, and an industry leading IESPP program with a 6-month look back feature. Find more information about all our benefits at the link below:
Benefits of working at Microchip
The annual base salary range for this position is N/A.*
- Range is dependent on numerous factors including job location, skills and experience.
To all recruitment agencies : Microchip Technology Inc. does not accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.
