Senior ASIC Verification Engineer, Networking IP
Location: Kanata, hybrid
Employment Type: Permanent, Full time
Join a highly experienced R&D team dedicated to developing intellectual property for advanced microcontrollers and microprocessors. This team focuses on creating a networking switch and network controller IP core that supports the latest TSN standards, forming the networking foundation for next generation microcontrollers, processors, and switches. The IP developed by this team underpins a product portfolio generating billions of dollars in annual revenue. The chips this team helps develop are found in vehicles, smart home devices, and the equipment used to manufacture everyday goods.
This role sits within a central design organization developing products across automotive, IoT, networking, and radio frequency markets. Expertise spans hardware engineering, including architecture, IP, and full SoC design.
Job Description
We are seeking a highly motivated Design Verification Engineer with a relentless drive to excel and make a significant impact. This team offers innovative thinking, engineering expertise, and sustained market leadership in embedded processing. You will work with advanced platforms delivered to major players in the automotive, industrial, edge, and telecommunication markets, featuring multiple processing cores and high performance networking accelerators integrated on the same silicon chip.
Responsibilities
- Architect, design, implement, and verify breakthrough Ethernet and networking IP to be integrated into next generation SoCs for automotive, industrial, and edge computing markets
- Own the architecture, design, and implementation of UVM verification of hardware IP and SoC products
- Perform thorough trade off analysis on performance and complexity
- Work closely with IP architecture, design, and verification teams on planning and execution to ensure the IP is delivered on time and with the highest quality
- Produce quality documentation for all phases of the project, including detailed IP functional and implementation specifications
- Build directed and random verification tests
- Debug test failures to determine root cause, working with architects and design engineers to resolve defects and correct issues
- Review functional and code coverage metrics, modifying or adding tests or constraining random tests to meet coverage requirements
- Proactively drive continuous improvement in design and verification methodology
Qualifications
- 10+ years of experience in IP and SoC products
- Thorough knowledge and expertise in System Verilog and UVM verification
- Strong understanding of IP and SoC development methodology and proficiency in verification tools
- Strong experience in EDA tools and scripting (Python, TCL, Perl, Makefile, Shell) used to build tools and flows for verification environments
- Strong experience architecting and implementing design verification infrastructure and executing the full verification cycle
- Experience with revision control systems like Git
- Familiarity with hardware and software implementation trade offs
- Focus on quality results with proven problem solving abilities
- Algorithm development experience
- Strong interpersonal, communication, and documentation skills
- Dynamic team player
- Bachelor's degree in Computer Science, Engineering, or a related field
Highly Desirable Skills
- Familiarity with formal and functional safety verification
- Knowledge of state of the art networking technologies, including TCP/IP protocols
- Experience with data products such as routers, bridges, and switches
- Security and cryptography experience
